Static random access memories (SRAMs) are sometimes used in preference to dynamic random access memories (DRAMs) because SRAMs have faster access times compared to DRAMs and do not need to be periodically “refreshed” to maintain a data state. Additionally, as will be explained in more detail below, data is typically stored by a SRAM cell by latching the data state. Since very little power is required to maintain a latched state, SRAM cells can be made to have very low power consumption.
FIG. 1 is a circuit diagram of a conventional 6-transistor (6T) SRAM cell 100. A pair of NMOS access transistors 112 and 114 allow complementary bit values D and/D on digit lines 116 and 118, respectively, to be read from and to be written to a storage circuit 120 of the SRAM cell 100. The storage circuit 120 includes NMOS pull-down transistors 122 and 126, which are coupled in a positive-feedback configuration with PMOS pull-up transistors 124 and 128. The SRAM cell 100 is bistable, that is, the SRAM cell 100 can have one of two stable data states, logic 1 or logic 0. Nodes A and B are the complementary inputs/outputs of the storage circuit 120, and the respective complementary logic values at these nodes represent the data state of the SRAM cell 100. For example, when the node A is at logic 1 and the node B is at logic 0, then the SRAM cell 100 is storing a logic 1. Conversely, when the node A is at logic 0 and the node B is at logic 1, then the SRAM cell 100 is storing a logic 0.
In operation, prior to a read operation, the digit lines 116 and 118 are equilibrated to approximately VDD. During a read of the SRAM cell 100, a word-line WL, which is coupled to the gates of the transistors 112 and 114, is driven to a voltage approximately equal to VDD to activate the transistors 112 and 114. By way of example, the voltage of VDD and a logic “1” is five volts and the voltage of VSS and a logic “0” is zero volts. Assuming that at the beginning of the read the SRAM cell 100 is storing a logic 0, the voltage level at the node A is 0 volts and the voltage level at the node B is 5 volts. In response to driving the WL to VDD, the NMOS transistor 112 couples the node A to the digit line 116, and the NMOS transistor 114 couples the node B to the digit line 118. Coupling the digit line 116 to the node A through the NMOS transistor 112 pulls down the voltage on the digit line 116 (e.g., 100-500 millivolts) to cause a sense amp (not shown) coupled to the digit lines 116 and 118 to read the SRAM cell 100 as storing a logic 0.
In operation during a write operation, for example, of a logic 1 to the SRAM cell 100, the WL is driven to a voltage approximately equal to VDD and the transistors 112 and 114 are activated as discussed above. The logic 1 is driven onto the digit line 116 and a logic 0 is driven onto the digit line 118. The transistor 112 couples the voltage of the digit line 116 to the node A, and the transistor 114 couples 0 volts from the digit line 118 to the node B. The low voltage on the node B turns OFF the NMOS transistor 126, and turns ON the PMOS transistor 128. As a result, the inactive NMOS transistor 126 allows the PMOS transistor 128 to pull the node A up to VDD. The voltage on the node A turns ON the NMOS transistor 122 and turns OFF the PMOS transistor 124, thus, allowing the NMOS transistor 122 to reinforce the logic 0 on the node B. Additionally, the VDD voltage coupled to the node A and the 0 volts coupled to the node B ensure that through the positive-feedback configuration the SRAM cell 100 will store a logic 1.
As previously discussed, reading data from a conventional SRAM cell and writing data to the SRAM cell work by activating opposing transistors of a pair of cross-coupled CMOS inverters. In the event the actual transistor characteristics of the NMOS 122, 126 or the PMOS 124, 128 deviate from expected transistor characteristics, the stability margin of the SRAM cell can be affected. Such shifts in transistor characteristics can be caused by different reasons, one of which is by process variations that occur during fabrication of the SRAM cells. If the actual transistor characteristics shift significantly enough, the SRAM cell can become monostable or read unstable instead of bistable.
A SRAM cell is monostable when it can store only one logic state instead of two logic states when the access transistors are in the OFF state. More specifically, with reference to FIG. 1, offset currents, typically on the order of picoamps (pA), often flow from the nodes A and B. These offset currents can be due to leakage currents, sub-threshold currents, or both, generated by the six transistors of the SRAM cell 100 when they are in an OFF state. To prevent these offset currents from causing the SRAM cell 100 to spontaneously change states, the PMOS transistors 124, 128 when ON must be able to provide currents that flow from VDD to the nodes A and B that are greater than or equal to these respective offset currents. For example, assume that the SRAM cell 100 is initially storing a logic 1 such that the voltage at the node A is approximately 5 volts and the voltage at the node B is approximately 0 volts, and that the total offset current drawn from the node A is 10 pA. If the PMOS transistor 128 allows only 5 pA to flow from VDD to the node A when ON due to a shift in its transistor characteristics, then the larger offset current will gradually discharge the parasitic capacitance (not shown) associated with the node A. Consequently, the voltage at the node A is lowered until the transistor 122 turns OFF. If the current through the PMOS transistor 124 is greater than the offset current drawn from the node B, then the voltage at the node B gradually increases until the transistor 126 turns ON and pulls the node A to zero volts. As a result, the SRAM cell 100 has only one stable state, that is, logic 0, when the access transistors 112 and 114 are OFF. Thus, even if a logic 1 is written, the SRAM cell 100 will eventually and spontaneously flip to a logic 0. Therefore, the SRAM cell 100 is monostable.
A SRAM cell is read unstable when the SRAM cell has only one stable logic state when the access transistors 112 and 114 are ON, as they are during a read operation. As a result, the SRAM cell 100 may be able to stably store a logic 1 or logic 0 that is written to it, but when the access transistors 112 and 114 are activated during a read (when there are no write voltages driven onto the digit lines 116 and 118), the SRAM cell 100 becomes read-monostable. If the logic state last written to the SRAM cell 100 is opposite the read-monostable state, then the SRAM cell 100 will spontaneously flip states and the incorrect data state will be read.
Therefore, there is a need for an alternative SRAM cell design that is more resilient than conventional SRAM cells to inadvertent bit flipping, such as monostability and read instability.